Control circuit and method for a flyback converter to compensate for an entry point of a burst mode

ABSTRACT

A control circuit and method are provided for a flyback converter converting an input voltage to an output voltage, to compensate for an entry point of a burst mode of the flyback converter, so that the entry point is not affected by the input voltage, and audible noise resulted from a higher input voltage is reduced without impacting the light load efficiency of the flyback converter.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 12/453,446, which was filed on May 12, 2009, and which claimsforeign priority to Taiwan application no. 097117743, which was filed onMay 14, 2008. The subject matter of each application is incorporatedherewith in its entirety.

FIELD OF THE INVENTION

The present invention is related generally to a flyback converter and,more particularly, to a control circuit and method for a flybackconverter.

BACKGROUND OF THE INVENTION

All electrical devices are required a power source for operation. Amongthe various types of power supplies, switching power converters arewidely used because they have better efficiency and provide suitableoutput modulation. However, when a switching power converter is underlight load conditions, its efficiency will reduce due to switching loss.To improve the efficiency at light load, a burst mode strategy isapplied to reduce the average switching frequency and save the switchingloss. FIG. 1 is a perspective diagram of a conventional current modeflyback converter 10, in which a rectifier 12 converts an AC voltage Vacinto a DC input voltage Vin, a controller 16 detects the current flowingthrough a power switch 18 to obtain a current sense signal Vcs, andprovides a control signal V_(GATE) according to the current sense signalVcs and a feedback signal Vcomp to switch the power switch 18, so as tohave a transformer 14 to convert the input voltage Vin into an outputvoltage Vo, and an opto-coupler 20 generates the feedback signal Vcompaccording to the output voltage Vo to feed back to the controller 16.The feedback signal Vcomp is a function of the output voltage Vo.

FIG. 2 is a perspective diagram of a portion of the controller 16 shownin FIG. 1, in which a burst circuit 22 has a hysteresis comparator 24 togenerate a mask signal Smask according to the feedback signal Vcomp anda preset voltage Burst_level to mask a clock CLK by an AND gate 26, anda pulse width modulation (PWM) circuit 28 has a comparator 30 to comparethe current sense signal Vcs with the feedback signal Vcomp to generatea comparison signal Sc, and a flip-flop 32 to generate the controlsignal V_(GATE) according to the output of the AND gate 26 and thecomparison signal Sc. FIG. 3 is waveform diagram of the flybackconverter 10 shown in FIG. 1, in which waveform 34 represents the load,waveform 36 represents the feedback signal Vcomp, and waveform 38represents the control signal V_(GATE). Referring to FIGS. 2 and 3, innormal operation, i.e. the load is heavy, as between time t1 and timet2, the feedback signal Vcomp is greater than voltages V_(BURH) andV_(BURL), as shown by the waveform 36, so that the clock CLK is notmasked, and in consequence the control signal V_(GATE) is continuouslyprovided to switch the power switch 18, as shown by the waveform 38. Thevoltages VBURH and VBURL are hysteresis boundaries generated by thehysteresis comparator 24 according to the voltage Burst_level. At timet2, the load turns from heavy to light so that the feedback signal Vcompbegins to drop. When the feedback signal Vcomp is lower than the voltageV_(BURL), as shown at time t3, the flyback converter 10 enters a burstmode, in which the mask signal Smask will switch to logic “0” when thefeedback signal Vcomp is lower than the voltage V_(BURL), thus maskingthe clock CLK, and the mask signal Smask will not switch to logic “1”until the feedback signal Vcomp is higher than the voltages V_(BURH), asshown at time t4. The clock CLK is released when the mask signal Smaskswitches to logic “1”. Hence, a burst cycle is generated to regulate theoutput voltage Vo and supply sufficient output power. One burst cycle isshown in FIG. 3 as between time t3 and time t5.

FIG. 4 is a perspective diagram of the current sense signals Vcs underdifferent input voltages Vin, in which waveform 40 represents thefeedback signal Vcomp, waveform 42 represents the current sense signalVcs corresponding to a high input voltage Vin, and waveform 44represents the current sense signal Vcs corresponding to a low inputvoltage Vin. FIG. 5 is a perspective diagram of burst mode entry pointsof load under different input voltages Vin, in which waveform 46represents the voltage V_(BRUH), waveform 48 represents the voltageV_(BRUL), waveform 50 represents the feedback signal Vcomp correspondingto a high input voltage Vin, and waveform 52 represents the feedbacksignal Vcomp corresponding to a low input voltage Vin followingdifferent output power conditions. Referring to FIG. 4 in conjunctionwith FIG. 1, if the input voltage Vin is a higher one, the current sensesignal Vcs increases at a higher speed, as shown by the waveform 42; ifthe input voltage Vin is a lower one, the current sense signal Vcsincreases at a lower speed, as shown by the waveform 44. After thecurrent sense signal Vcs reaches the level of the feedback signal Vcomp,a propagation delay time Tp due to the delay in signal propagation mustelapse before the power switch 18 is turned off. In addition, since thecurrent sense signal Vcs increases at a higher speed under a higherinput voltage Vin, the current sense signal Vcs corresponding to thehigher input voltage Vin has a higher peak than the current sense signalVcs corresponding to the lower input voltage Vin, if the propagationdelay Tp is a constant duration. In other words, the peak of the currentI1 in the primary side of the transformer 14 is higher under the higherinput voltage Vin than under the lower input voltage Vin following thesame Vcomp level. In the burst mode, the current I1 has a minimum pulse:

I1min=(Burst_level/Rcs)+(Vin/Lm)×Tp,  [1]

where Lm is magnetizing inductance. After the flyback converter 10enters the burst mode, the frequency of each burst cycle may fall withinan audible noise range of 100 Hz to 20 kHz, such that the higher thecurrent I1 is, the louder the audible noise will be. Moreover, thefeedback signal Vcomp varies with the peak value of the current I1.Referring to FIG. 5, if the input voltage Vin is higher, the peak valueof the current I1 is higher and in consequence the feedback signal Vcompis lower, as shown by the waveform 50. Hence, the flyback converter 10enters the burst mode earlier. On the contrary, if the input voltage Vinis lower, the peak value of the current I1 is lower so that the feedbacksignal Vcomp is higher, as shown by the waveform 52. As a result, theentry point B of the burst mode under the lower input voltage Vin comeslater than the entry point A of the burst mode under the higher inputvoltage Vin.

Therefore, it is desired an apparatus and method to compensate thepropagation delay and thus compensate for the entry point of the burstmode.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a control circuit andmethod for a flyback converter to compensate the propagation delay andthereby compensate for the entry point of the burst mode of the flybackconverter.

According to the present invention, a control circuit for a flybackconverter including a transformer connected with a power switch switchedby a control signal for the transformer to convert an input voltage intoan output voltage, comprises a burst circuit to determine whether tocontrol the flyback converter to enter a burst mode according to afeedback signal and a preset value, a compensator to compensate thefeedback signal to generate a compensated feedback signal, and a pulsewidth modulation circuit to generate the control signal according to thecompensated feedback signal and a current sense signal. The feedbacksignal is a function of the output voltage, and the current sense signalis a function of a current flowing through the power switch. Thecompensator compensates the feedback signal to prevent the entry pointof the burst mode from being affected by the input voltage.

According to the present invention, a control circuit for a flybackconverter including a transformer connected with a power switch switchedby a control signal for the transformer to convert an input voltage intoan output voltage, comprises a burst circuit to determine whether tocontrol the flyback converter to enter a burst mode according to afeedback signal and a preset value, a compensator to compensate acurrent sense signal to generate a compensated current sense signal, anda pulse width modulation circuit to generate the control signalaccording to the feedback signal and the compensated current sensesignal. The feedback signal is a function of the output voltage, and thecurrent sense signal is a function of a current flowing through thepower switch. The compensator compensates the current sense signal toprevent the entry point of the burst mode from being affected by theinput voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will become apparent to those skilled in the art uponconsideration of the following description of the preferred embodimentsof the present invention taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a perspective diagram of a conventional current mode flybackconverter;

FIG. 2 is a perspective diagram of a portion of the controller shown inFIG. 1;

FIG. 3 is waveform diagram of the flyback converter shown in FIG. 1;

FIG. 4 is a perspective diagram of current sense signals under differentinput voltages;

FIG. 5 is a perspective diagram of burst mode entry points underdifferent input voltages;

FIG. 6 is a perspective diagram of a first embodiment according to thepresent invention;

FIG. 7 is a perspective diagram of the details of the control circuitshown in FIG. 6;

FIG. 8 shows a waveform diagram of a sawtooth wave;

FIG. 9 is a waveform diagram of a compensated feedback signal and thecurrent sense signals Vcs under different input voltages; and

FIG. 10 is a perspective diagram of a second embodiment according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 6 is a perspective diagram of a first embodiment according to thepresent invention. The controller 16 shown in FIG. 2 is now replaced bythe control circuit 54 shown in FIG. 6 to be used in FIG. 1. In thecontrol circuit 54, a compensator 56 compensates the feedback signalVcomp to generate a compensated feedback signal Vcomp_c, a burst circuit58 generates a mask signal Smask according to the feedback signal Vcompand the preset voltage Burst_level to determine whether to control theflyback converter 10 to enter the burst mode, and a PWM circuit 60generates the control signal V_(GATE) according to the current sensesignal Vcs, the compensated feedback signal Vcomp_c, and the mask signalSmask, to switch the power switch 18. FIG. 7 is a perspective diagram ofthe details of the control circuit 54 shown in FIG. 6. As shown in FIG.7, the compensator 56 includes an adder 62 having a positive input 622to receive the feedback signal Vcomp, a negative input 624 to receive asawtooth wave Sramp synchronous with the clock CLK, and an output 626 togenerate the compensated feedback signal Vcomp_c. Since the higher theinput voltage Vin is, the greater the propagation delay and the higherthe peak of the current I1 will be, the sawtooth wave Sramp is deductedfrom the feedback signal Vcomp so that the compensated feedback signalVcomp_c has a right slope. The burst circuit 58 includes a hysteresiscomparator 64 to generate the mask signal Smask according to thefeedback signal Vcomp and the voltage Burst_level, and provide the masksignal Smask to an AND gate 66 to mask the clock CLK and in consequencereduce the number of times the power switch 18 is to be switched. ThePWM circuit 60 includes a comparator 68 to compare the current sensesignal Vcs with the compensated feedback signal Vcomp_c to generate acomparison signal S2, and a flip-flop 70 having a set input S to receivethe output S1 of the AND gate 66, a reset input R to receive the signalS2, and an output Q to generate the control signal V_(GATE).

FIG. 8 is a waveform diagram of the sawtooth wave Sramp, which has awidth W equal to 6.25% of the switching cycle of the power switch 18 anda peak-to-valley difference H approximately equal to 0.15 V. FIG. 9 is awaveform diagram of the compensated feedback signal Vcomp_c and thecurrent sense signals Vcs under different input voltages Vin, in whichwaveform 72 represents the compensated feedback signal Vcomp_c, waveform74 represents the current sense signal Vcs corresponding to a higherinput voltage Vin, and waveform 76 represents the current sense signalVcs corresponding to a lower input voltage Vin. In this embodiment, thedifference between the highest value and the lowest value of thecompensated feedback signal Vcomp_c is about 0.15 V, and the compensatedfeedback signal Vcomp_c has a right slope. If the input voltage Vin is ahigher one, the current sense signal Vcs increases at a higher speed, asshown by the waveform 74, and consequently the compensated feedbacksignal Vcomp_c is lower for the current sense signal Vcs under thehigher input voltage Vin to reach. On the contrary, if the input voltageVin is a lower one, the current sense signal Vcs increases at a lowerspeed, as shown by the waveform 76, so that the compensated feedbacksignal Vcomp_c is higher for the current sense signal Vcs under thelower input voltage Vin to reach. Since the current sense signal Vcsunder the higher input voltage Vin only has to increase to the lowerlevel to reach the compensated feedback signal Vcomp_c, and the currentsense signal Vcs under the lower input voltage Vin has to increase tothe higher level to reach the compensated feedback signal Vcomp_c, thepeak values of the current sense signals Vcs in both cases aresubstantially the same after the propagation delay Tp. In other words,be the input voltage Vin high or low, the current I1 flowing through thepower switch 18 will remain substantially the same, and the effect ofthe propagation delay is thus minimized.

After the feedback signal Vcomp is compensated with the sawtooth waveSramp, the current I1 flowing through the power switch 18 underdifferent input voltages Vin stays substantially the same. As a result,the entry point of the burst mode no longer changes with the variationof the input voltage Vin, and the propagation delay is reduced tominimum. Besides, in the burst mode, the peak value of the current I1will not rise because of a higher input voltage Vin, so that the audiblenoise is decreased.

FIG. 10 is a perspective diagram of a second embodiment according to thepresent invention, in which a control circuit 80 also includes the burstcircuit 58, the PWM circuit 60 and the AND gate 66. The control circuit80 further includes a compensator 82 to compensate the current sensesignal Vcs to generate a compensated current sense signal Vcs_c. Thecomparator 68 in the PWM circuit 60 compares the compensated currentsense signal Vcs_c with the feedback signal Vcomp to generate the signal52, which is then supplied to the reset input R of the flip-flop 70. Thecompensator 82 includes an adder 84 having two positive inputs 842 and844 to receive the current sense signal Vcs and the sawtooth wave Sramprespectively, and an output 846 to provide the compensated current sensesignal Vcs_c. Similarly, after the current sense signal Vcs iscompensated with the sawtooth wave Sramp, the peak value of the currentI1 flowing through the power switch 18 will remain substantially thesame under different input voltages Vin, so that the entry point of theburst mode will not change as the input voltage Vin varies.

While the present invention has been described in conjunction withpreferred embodiments thereof, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart Accordingly, it is intended to embrace all such alternatives,modifications and variations that fall within the spirit and scopethereof as set forth in the appended claims.

What is claimed is:
 1. A control circuit for a flyback converterincluding a transformer connected with a power switch switched by acontrol signal for the transformer to convert an input voltage into anoutput voltage, the control circuit comprising: a compensatorcompensating a feedback signal with a sawtooth wave to generate acompensated feedback signal, the sawtooth wave independent of the inputvoltage, the feedback signal being a function of the output voltage; anda pulse width modulation circuit connected to the compensator togenerate the control signal according to the compensated feedback signaland a current sense signal, the current sense signal being a function ofa current flowing through the power switch.
 2. The control circuit ofclaim 1, wherein the pulse width modulation circuit comprises: acomparator connected to the compensator to compare the compensatedfeedback signal with the current sense signal to generate a comparisonsignal; and a flip-flop connected to the comparator to generate thecontrol signal according to the comparison signal and a clock.
 3. Thecontrol circuit of claim 1, wherein the compensator comprises an adderhaving a positive input to receive the feedback signal, a negative inputto receive the sawtooth wave, and an output to provide the compensatedfeedback signal.
 4. The control circuit of claim 1, further comprising aburst circuit to determine whether to control the flyback converter toenter a burst mode according to the feedback signal and a preset value.5. The control circuit of claim 4, wherein the burst circuit comprises acomparator to generate a mask signal according to the feedback signaland the preset value to reduce the number of times the power switch isto be switched.
 6. The control circuit of claim 5, wherein thecomparator is a hysteresis comparator.
 7. The control circuit of claim4, wherein the sawtooth wave is used to stabilize an entry point of theburst mode.